도닦는공돌이

9 FORMATS WITH 7-BIT ADDRESSES

Data transfers follow the format shown in Fig.10. After the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a ‘zero’ indicates a transmission (WRITE), a ‘one’ ndicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer

Possible data transfer formats are:

· Master-transmitter transmits to slave-receiver. The transfer direction is not changed (see Fig.11).

· Master reads slave immediately after first byte (see Fig.12). At the moment of the first acknowledge, the master- transmitter becomes a master- receiver and the slave-receiver becomes a slave-transmitter. This first acknowledge is still generated by the slave. The STOP condition is generated by the master, which has previously sent a not-acknowledge (A).

· Combined format (see Fig.13). During a change of direction within a transfer, the START condition and the slave address are both repeated, but with the R/W bit reversed. If a master receiver sends a repeated START condition, it has previously sent a not-acknowledge (A).

NOTES:

1. Combined formats can be used, for example, to control a serial memory. During the first data byte, the internal memory location has to be written. After the START condition and slave address is repeated, data can be transferred.

2. All decisions on auto-increment or decrement of previously accessed memory locations etc. are taken by the designer of the device.

3. Each byte is followed by an acknowledgment bit as indicated by the A or A blocks in the sequence.

4. I2C-bus compatible devices must reset their bus logic on receipt of a START or repeated START condition such that they all anticipate the sending of a slaveaddress, even if these START conditions are not positioned according to the proper format.

5. A START condition immediately followed by a STOP , condition (void message) is an illegal format.

위의 Fig11,12,13 의 형태로 데이터를 전송합니다.

-> 요약하면, DATA는 반드시 8bit 크기로 보내어진다. 그리고 Slave가 data를 다 수신하지 못했다면 slave는 SCL신호를 LOW로 유지함으로써 Data를 모두 전달 받을수가 있다. (그래서 신호선이 풀업저항설계가 되어있는 것.) //

[통신의 송수신 순서]

1. SDA,SCL 둘다 HIGH 상태인가?  - 그렇다면 Bus는 비어있다.

2. 시작비트를 보낸다. (SCL: : HIGH, SDA : LOW)

3. 7bit의 주소값을 보내고 1bit의 R/W를 보낸다.

4. ACK를 수신하기 위해서 SDA방향을 마스터기준으로 INPUT으로 변경하고 SCL만 출력한다 (클럭신호만 아웃)

5. ACk왔다면 실어보낼 데이터를 전송한다. (1byte)

6. ACK를 수신하기 위해서 SDA의 방향을 마스터기준으로 INPUT으로 또다시 변경하고 SCL만을 출력

7. 더이상 전송할 데이터가 없다면 SDA와 SCL을 HIGH상태로 변경시킨다.

8. 정지비트를 보낸다.

[인터넷에 있는 데이터 송수신 예제입니다. ] : southlife님의 블로그참조 http://southlife.tistory.com/49 

4 THE I2C-BUS CONCEPT

The I2C-bus supports any IC fabrication process (NMOS,CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether it’s a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. Inaddition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table 1). A master is the device which initiates a data transfer on the bus and generates the clock

signals to permit that transfer. At that time, any device addressed is considered a slave.

Table 1 Definition of I2C-bus terminology

The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually micro-controllers, let’s consider the case of a data transfer between two microcontrollers connected to the I2C-bus (see Fig.2).

This highlights the master-slave and receiver-transmitter relationships to be found on the I2C-bus. It should be noted

that these relationships are not permanent, but only depend on the direction of data transfer at that time. The

transfer of data would proceed as follows:

1) Suppose microcontroller A wants to send information to microcontroller B:

· microcontroller A (master), addresses microcontroller B (slave)

· microcontroller A (master-transmitter), sends data to microcontroller B (slave- receiver)

· microcontroller A terminates the transfer

2) If microcontroller A wants to receive information from microcontroller B:

· microcontroller A (master) addresses microcontroller B (slave)

· microcontroller A (master- receiver) receives data frommicrocontroller B (slave- transmitter)

· microcontroller A terminates the transfer.

Even in this case, the master (microcontroller A) generates the timing and terminates the transfer.

The possibility of connecting more than one microcontroller to the I2C-bus means that more than one

master could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event -

an arbitration procedure has been developed. This procedure relies on the wired-AND connection of all I2C

interfaces to the I2C-bus.

If two or more masters try to put information onto the bus, the first to produce a ‘one’ when the other produces a

‘zero’ will lose the arbitration. The clock signals during arbitration are a synchronized combination of the clocks

generated by the masters using the wired-AND connection to the SCL line

Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line, or by another master when arbitration occurs.

5 GENERAL CHARACTERISTICS

Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a current-source or pull-up resistor (see Fig.3). When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the I2C-bus can be transferred at rates of up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. The number of

interfaces connected to the bus is solely dependent on the bus capacitance limit of 400 pF. For information on High-speed mode master devices

6 BIT TRANSFER

Due to the variety of different technology devices (CMOS,NMOS, bipolar) which can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of VDD (see Section 15 for electrical specifications). One clock pulse is generated for each data bit transferred.

6.1 Data validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Fig.4).

6.2 START and STOP conditions

Within the procedure of the I2C-bus, unique situations arise which are defined as START (S) and STOP (P) conditions (see Fig.5).

A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered to be busy after the START

condition. The bus is considered to be free again a certain time after the STOP condition. This bus free situation is

specified in Section 15. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical (see Fig. 10). For the remainder of this document, therefore, the S symbol will be used as a generic term to represent both the START and repeated START

conditions, unless Sr is particularly relevant. Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition.

-> START는 위의 파형과 같이 SCL이 High신호일대 SDA가 Falling 하는 경우로 slave에게 protocol이 시작됨을 알린다.

-> STOP는 SCL이 HIGH일때 SDA가 Rising 하는 경우로 Slave에게 protocol이 종료됨을 알린다.

즉, 둘다 SCL이 High일때 시작과 끝을 상승/하강 엣지로 Slave에게 알리는것이다. 그럼 반대로 SCL이 LOW레벨일때는 어떤동작을 할까? 아래의 내용을 보자.

7 TRANSFERRING DATA

7.1 Byte format

Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (see Fig.6). 

If a slave can’t receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then

continues when the slave is ready for another byte of data and releases clock line SCL.

In some cases, it’s permitted to use a different format from the I2C-bus format (for CBUS compatible devices for example). A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte. In this case, no acknowledge is generated. 

7.2 Acknowledge

Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse (see Fig.7). Of

course, set-up and hold times  must also be taken into account. Usually, a receiver which has been addressed is obliged to

generate an acknowledge after each byte has been received, except when the message starts with a CBUS

address. When a slave doesn’t acknowledge the slave address (for example, it’s unable to receive or transmit because it’s

performing some real-time function), the data line must be left HIGH by the slave. The master can then generate

either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.

If a slave-receiver does acknowledge the slave address but, some time later in the transfer cannot receive any

more data bytes, the master must again abort the transfer. This is indicated by the slave generating the

not-acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates a

STOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signal the end of data to the slave- transmitter by not generating

an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line

to allow the master to generate a STOP or repeated START condition.

-> DATA 는 SCL(클럭)이 LOW일때 SDA의 값이 변할수 있으며 SCL이 HIGH상태일대 SDA의 값이 유효하다. 

(SCL이 LOW일때 SDA의 신호를 변경할수있다는 뜻이다.)

(SCL이 HIGH일때 SDA신호가 일정해야지만 DATA값이 유효하는 뜻이기도 하다)

즉, START 비트가 출력되었고 다음 클럭의 HIGH신호일때 마스터가 SDA값을 읽거나 쓸수가 있다는 뜻이다.

또한 DATA bits는 ACK 신호와 R/W신호를 포함하고 있다.  

R/W신호 High 상태 = READ

R/W신호 LOW 상태 = WRITE

▶그렇다면? 어떻게 2개의 WIRE로 충돌없이 통신이 가능한것인가???

= 이는 통신시작을 알리는 START bit는 SDA,SCL 이 모두 HIGH일때만 발생하기때문에 이 조건이 만족하지 않으면 시작하지 않기 때문이다. 

▶ PULL-UP  저항은 왜 필요한것인가?

= 버스와 물려있는 다른 device간의 입출력 전압차를 상관없이 하나의 VCC레벨로 통합시켜버린다. (물론 적당히;;ㅋㅋ)

또한, 항상 SDA와 SCL이 HIGH상태로 유지하도록 만들어서 둘다 HIGH이면 버스상에 신호가 없으며 지금 IC2를 사용할수있는 의미가 된다.

▶ ACK신호는 왜 사용하는가?

= 데이터전달이 잘 되었는지를 확인하는데 그 목적이 있으며, 이는 반드시 처리해야하는 의무성을 지닌다.

다음 챕터의 데이터송수신의 과정을 읽게되면 이해하게 될것입니다.

The I2C-bus specification

1 PREFACE (서문)

1.1 Version 1.0 - 1992

This version of the 1992 I2C-bus specification includes the following modifications:

· Programming of a slave address by software has been omitted.

  The realization of this feature is rather complicated and has not been used.

· The “low-speed mode” has been omitted. This mode is, in fact, a subset of the total I2C-bus specification and need not be specified explicitly.

· The Fast-mode is added. This allows a fourfold increase of the bit rate up to 400 kbit/s. Fast-mode devices are downwards compatible i.e. they can be used in a 0 to 100 kbit/s I2C-bus system.

· 10-bit addressing is added. This allows 1024 additional slave addresses.

· Slope control and input filtering for Fast-mode devices is specified to improve the EMC behaviour.

NOTE: Neither the 100 kbit/s I2C-bus system nor the 100 kbit/s devices have been changed.

1.2 Version 2.0 - 1998

The I2C-bus has become a de facto world standard that is now implemented in over 1000 different ICs and licensed to more than 50 companies. Many of today’s applications, however, require higher bus speeds and lower supply voltages. This updated version of the I2C-bus specification meets those requirements and includes the following modifications:

· The High-speed mode (Hs-mode) is added. This allows an increase in the bit rate up to 3.4 Mbit/s. Hs-mode devices can be mixed with Fast- and Standard-mode devices on the one I2C-bus system with bit rates from 0 to 3.4 Mbit/s.

· The low output level and hysteresis of devices with a supply voltage of 2 V and below has been adapted to meet the required noise margins and to remain compatible with higher supply voltage devices.

· The 0.6 V at 6 mA requirement for the output stages of Fast-mode devices has been omitted.

· The fixed input levels for new devices are replaced by bus voltage-related levels. 

· Application information for bi-directional level shifter is added.

1.3 Version 2.1 - 2000

Version 2.1 of the I2C-bus specification includes the following minor modifications:

· After a repeated START condition in Hs-mode, it is possible to stretch the clock signal SCLH (see Section 13.2 and Figs 22, 25 and 32). · Some timing parameters in Hs-mode have been relaxed (see Tables 6 and 7).

2 THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS

In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes:

· Some intelligent control, usually a single-chip microcontroller

· General-purpose circuits like LCD drivers, remote I/O ports, RAM, EEPROM, or data converters

· Application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, or DTMF generators for telephones with tone dialling. To exploit these similarities to the benefit of both systems designers and quipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips developed a simple bi-directional 2-wire bus for efficient inter-IC control. This bus is called the Inter IC or I2C-bus.

At present, Philips’ IC range includes more than 150 CMOS and bipolar I2C-bus compatible types for performing functions in all three of the previously mentioned categories. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus. This design concept solves the many interfacing problems encountered when designing digital control circuits. 

Here are some of the features of the I2C-bus:

· Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL)

· Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers

· It’s a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer · Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode

· On-chip filtering rejects spikes on the bus data line to preserve data integrity

· The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400 pF.

Figure 1 shows two examples of I2C-bus applications.

 2.1 Designer benefits

I2C-bus compatible ICs allow a system design to rapidly progress directly from a functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the I2C-bus without any additional external interfacing, they allow a prototype system to be modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.

Here are some of the features of I2C-bus compatible ICs which are particularly attractive to designers:

· Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block

diagram to final schematic.

· No need to design bus interfaces because the I2C-bus interface is already integrated on-chip.

· Integrated addressing and data-transfer protocol allow systems to be completely software-defined

· The same IC types can often be used in many different applications

· Design-time reduces as designers quickly become familiar with the frequently used functional blocks represented by I2C-bus compatible ICs

· ICs can be added to or removed from a system without affecting any other circuits on the bus

· Fault diagnosis and debugging are simple; malfunctions can be immediately traced

· Software development time can be reduced by assembling a library of reusable software modules.

In addition to these advantages, the CMOS ICs in the I2C-bus compatible range offer designers special features which are particularly attractive for portable equipment and battery-backed systems.

They all have:

· Extremely low current consumption

· High noise immunity

· Wide supply voltage range

· Wide operating temperature range.

2.2 Manufacturer benefits

I2C-bus compatible ICs don’t only assist designers, they also give a wide range of benefits to equipment

manufacturers because:

· The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pins and there are

not so many PCB tracks; result - smaller and less expensive PCBs

· The completely integrated I2C-bus protocol eliminates the need for address decoders and other ‘glue logic’

· The multi-master capability of the I2C-bus allows rapid testing and alignment of end-user equipment via external connections to an assembly-line

· The availability of I2C-bus compatible ICs in SO (smalloutline), VSO (very small outline) as well as DIL packages reduces space requirements even more.

These are just some of the benefits. In addition, I2C-bus compatible ICs increase system design flexibility by allowing simple construction of equipment variants and easy upgrading to keep designs up-to-date. In this way, an entire family of equipment can be developed around abasic model. Upgrades for new equipment, or enhanced-feature models (i.e. extended memory, remote control, etc.) can then be produced simply by clipping the appropriate ICs onto the bus. If a larger ROM is needed,

it’s simply a matter of selecting a micro-controller with a larger ROM from our comprehensive range. As new ICs supersede older ones, it’s easy to add new features to equipment or to increase its performance by simply unclipping the outdated IC from the bus and clipping on its successor.

3 INTRODUCTION TO THE I2C-BUS SPECIFICATION

For 8-bit oriented digital control applications, such as those requiring microcontrollers, certain design criteria can be

established:

· A complete system usually consists of at least one microcontroller and other peripheral devices such as memories and I/O expanders

· The cost of connecting the various devices within the system must be minimized 

· A system that performs a control function doesn’t require high-speed data transfer 

· Overall efficiency depends on the devices chosen and the nature of the interconnecting bus structure.

To produce a system to satisfy these criteria, a serial bus structure is needed. Although serial buses don’t have the

throughput capability of parallel buses, they do require less wiring and fewer IC connecting pins. However, a bus is not merely an interconnecting wire, it embodies all the formats and procedures for communication within the system.

Devices communicating with each other on a serial bus must have some form of protocol which avoids all possibilities of confusion, data loss and blockage of information. Fast devices must be able to communicate with slow devices. The system must not be dependent on the devices connected to it, otherwise modifications or improvements would be impossible. 

A procedure has also to be devised to decide which device will be in control of the bus and when. And, if different devices with different clock speeds are connected to the bus, the bus clock source must be defined. All these criteria are involved in

the specification of the I2C-bus.

결론적으로 2000년도에 발표된 2.1버전의 특징만 아시면 됩니다.

간단하게 요약하자면 ,

-오직 2가닥의 와이어만 필요합니다 (SDA-Serial Data Line, SCL-Serial Clock Line) 또한 인터페이스는 칩에 내장되어있기에 별다른 디자인이 필요하지 않습니다.

-SCL은 마스터에서 클럭소스를 OUT하는 선이며 SDA는 SCL의 클럭에 완벽히 동기화되어 실제 data가 송수신됩니다.

-Bus에 연결된 master와 slave는 소프트웨어적으로 adress접근이 가능하다면 완벽하게 연결되며 제어가 됩니다.

-다수의 마스터가 연결될수가 있으며 장치간 충돌이 있어도 감지가 가능합니다. 또한 2개이상의 마스터를 초기화해도 통신이 가능합니다.

-시리얼 8비트 데이터통신은 일반모드에서 100kbps의 속도를 FAST모드에서 200kbps, Highspeed모드에서 3.4Mbps의 속도를 가집니다.

-단일칩 필러터링으로 버스에서 발생할수있는 노이즈를 차단할수있습니다

-최대 연결이 가능한 버스는 커패시턴스가 400pF이 넘지않는다면 IC를 계속 연결할수있습니다. ATmega를 예로들면 최대 연결이 가능한 IC는 128개로 제한하고 있습니다. 이는 주소값이 7bit 가지므로 2^7=128 의 이론값에서 나온것입니다.

일단 이정도 하시면 사용에 문제는 없습니다.

ISR(INT0_vect){}

ISR(INT1_vect){}

ISR(INT2_vect){}

ISR(INT3_vect){}

ISR(INT4_vect){}

ISR(INT5_vect){}

ISR(INT6_vect){}

ISR(INT7_vect){}

ISR(TIMER0_OVF_vect){}

ISR(TIMER0_COMP_vect){}

ISR(TIMER1_OVF_vect){}

ISR(TIMER1_CAPT_vect){}

ISR(TIMER1_COMPA_vect){}

ISR(TIMER1_COMPB_vect){}

ISR(TIMER1_COMPC_vect){}

ISR(TIMER2_OVF_vect){}

ISR(TIMER2_COMP_vect){}

ISR(TIMER3_OVF_vect){}

ISR(TIMER3_CAPT_vect){}

ISR(TIMER3_COMPA_vect){}

ISR(TIMER3_COMPB_vect){}

ISR(TIMER3_COMPC_vect){}

ISR(USART0_RX_vect){}

ISR(USART0_UDRE_vect){}

ISR(USART0_TX_vect){}

ISR(USART1_RX_vect){}

ISR(USART1_UDRE_vect){}

ISR(USART1_TX_vect){}

ISR(ADC_vect){}

ISR(ANALOG_COMP_vect){}

ISR(EE_READY_vect){}

ISR(SPI_STC_vect){}

ISR(TWI_vect){}

ISR(SPM_READY_vect){}

초보시절 ATmega의 FUSE셋팅을 잘못입력하여 클럭을 죽여버리는경우가 종종 생깁니다.

이런경우 ATmega128에 외부클럭 1Mhz를 Xtal1핀(24)에 인가하면 AVR studio의  퓨즈세팅에 다시 진입할수 있습니다.

결론적으로 인공호흡적은 외부클럭 1Mhz를 어떻게 만들어 낼것인가라는 문제로 귀결됩니다.

1. 만약 펑션제너레이터가 있으시다면 문제는 간단합니다. 그냥 입력하십시요. (GND는 공통으로 물려주십시요) 

2. 다른 정상적인 ATmega128로 타이머/카운터로 1Mhz의 신호가 출력되도록 분주시켜서 클럭을 인가합니다.

3. OSC 1~4Mhz를 구매하여 Atmega128의 Xtal1핀에 인가합니다.

[구구절절설명하는 인공호흡개념..]

인공호흡이라는 개념을 이해하기 위해선 ATmega128과 같은 MCU는 일종의 심장을 가지고 있다고 생각하시면 쉽습니다. MCU의 모든 명령은 클럭과 함께 수행됩니다. 또한 ATmega는 초기 공장에서 출하될때 1Mhz의 내부클럭으로 설정되어 자체내에 가지고있는 오실레이터로 클럭을 만들어서 사용합니다. 문제는 내가 외부적으로 크리스탈/레조레이터나 오실레이터로 아트메가의 XTAL1~2핀에 클럭을 인가해주었때 발생합니다. 외부 클럭인가후 AVR Studio의 FUST셋팅으로 지금 ATmega가 사용할 클럭이 "외부클럭신호이며 어느정도의 속도를 지니고있다"라고 설정을 하게 됩니다만..이때 외부클럭회로가 틀렸거나 설정값과 다른 주파수의 클럭신호가 입력되고 있다면 ATmega는 클럭을 잃어버리고 ISP,JTAG등..프로그램주입 및 PC를 통해서 진입할수가 없게 됩니다. 당연히 진입할때 클럭신호를 사용하여 명령을 주고 받는데 이것이 꼬이게 됨으로 일어나게 되는 현상입니다.  

그래서 공장출하 당시의 클럭주파수인 1Mhz 신호를 XTAL1핀에만 인가하게되면 초기상태의 내부1Mhz OSC로 동작하도록 다시 설정할수가 있으며 이를 우리는 "인공호흡법"과 유사하여 그렇게 부르고 있습니다.

[순서]

1. AVR studio의 FUSE셋팅 설정화면으로 들어갑니다 (당연히 다른 컴파일러도 가능하겠죠?)

2. 죽어있는 ATmega에 외부클럭 1MHz를 인가합니다 (XTAL1핀에만, 입력클럭소소의 GND는 ATmega와 같아야겠죠?)

3. FUSE셋팅의 클럭설정을 내부 1MHz OSC로 동작하도록 설정(Program)하고 외부클럭을 제거합니다.

4. 끝났습니다. 이제 다시 ATmega는 내부클럭을 사용하고있습니다. 다음번에 실수하지 않으시면 됩니다~!

물론 이렇게 하여도..살아나지(?)않는 ATmega도 존재합니다...어쩔수없이..그런경우는..이미 운명하셨다고 생각하시면 됩니다.. 

아래의 자료는 뉴티씨사의 외부 오실레이터를 이용한 ATmega 인공호흡법 자료입니다. 참고하세요.

AVR 기초강좌-인공호흡편.pdf

PNP switching transistor : High-speed switching in industrial applications.

2N3906(PNP).pdf

본문스크랩 http://worynim.tistory.com/entry/Fuse-bit

처음에 퓨즈비트를 공부할때 혹시나 잘못건드리면 망가진다는 얘기에 두근두근 하면서 퓨즈비트를 건드린 기억이 있다.

퓨즈비트는 시스템의 설정을 하는 비트로 mega128 에서는 3바이트로  되어 있다.
클럭을 설정한다거나 워치독타이머를 허용한다거나. jtag 허용한다거나.. 부트로더 관련 설정을 한다거나.. 등등등의 역할 을 한다.

시중의 여러 책들을 보면 아주 잘 설명이 되어 있으므로 이번 글에서는 간단히 설정하는 법을 알아 보자.

우선.. mega128을 기준으로 한다.
퓨즈비트를 설정할때 가장 중요한 것은.. 클럭이다. 클럭설정을 잘 못하면..  아래와 같은 창이 뜨면서 인공호흡을 해야 하는 상황이 온다.

(연결이나 isp 에 아무 문제가 없는데 아래처럼 뜬다면 아주 귀찮다.)

0.9Mhz 이하면 Low Freq 을
0.9Mhz~3Mhz 면 Medium 을 선택
3Mhz 이상이면 High 을 선택하고

레조네이터면 Start-up time: 1K CK 를 선택
크리스탈이면 Start-up time: 16K CK 를 선택
추가 지연 시간은 잘 모르겠으면 64ms 를 선택하자.

잘 모르겠으면 3Mhz 이상의 크리스탈을 달았다면 그냥 가장 아래에 있는 것을 고르시면 별 문제 없다.


참고로 아래와 같은 ISP 모드 에러창이 뜨는 상황과 해결책을 알아보자.  

1. ISP 핀 연결이 정확하게 되어 있지 않을때
선을 반대로 꼽았다던가.. 그러면 저런 에러가 뜬다. 
 >>선을 제대로 연결하자

2. AVR 의 ISP핀(SPI핀)들을 다른 디바이스와 공유할때  
ISP로 다운로드 해야 하는데.. 이 핀에 다른 디바이스(다른 IC 나 저항이나 등등등) 이 물려있다면.. 신호가 충돌해서 저런 에러가 뜰 수 있다. 
>> ISP 신호선은 다이렉트로 다른 디바이스로 가는 신호선들은 1K옴 정도의 직렬저항을 달아보자. 안되면 다른 포트로 옮기자.

3. ISP 주파수가  AVR의 시스템주파수(클럭)의 1/4 이상일때
>> 이상이라면 이하로 설정해 주면 됩니다. 컴파일러에서 설정해 주는 옵션이 있다. (230K 정도로 설정해서 해보자.)

4. 퓨즈비트가 잘못 설정 되어있을 때 
>> 인공호흡을 해서 퓨즈비트를 제대로 설정해 준다.

::: Switching Regulator, 3A/5V DC,입력4~40V,스위칭주파수52000 ::: 

Datasheet는 카테고리- 아무도가르쳐주지않는-DaTtaSheet(모음)에 있습니다 ^^

정전압 5V가 필요한 디바이스는 참 많은것 같습니다.

또한 5V전압과 동시에 1A이상의 전류가 필요한 시스템도 많구요...

아래의 IC를 사용하시면 최대 3A까지 전류를 안정적으로 뽑아내실수가 있습니다.

방열판을 달아주시면 더 좋구요~ 

--------------------------------------------------------

Features

3.3V, 5V, 12V, 15V, and adjustable output versions

Adjustable version output voltage range, 1.23V to 37V (57V for HV version) ±4% max over line and load conditions

Guaranteed 3A output current

Wide input voltage range, 40V up to 60V for HV version

Requires only 4 external components

52 kHz fixed frequency internal oscillator

TTL shutdown capability, low power standby mode

High efficiency

Uses readily available standard inductors

Thermal shutdown and current limit protection

P+ Product Enhancement tested

Applications

Simple high-efficiency step-down (buck) regulator

Efficient pre-regulator for linear regulators

On-card switching regulators

Positive to negative converter (Buck-Boost)

Ordering Information

Package Type : TO-220

Operating Temperature Range : -40℃ to +125℃

보통 3.3V를 많이 쓰시진 않지만..간혹가다 몇종류의 센서나 블루투스 모듈 전원으로 필요할때가 있습니다.

이럴때 5V를 인가해버리면 해당 IC는 곧 운명할것입니다..ㅠㅠ 

귀찮더라도 반드시 입력전압을 지켜서 사용하시기 바랍니다.

아래는 대표적으로 많이 사용하는 전원회로입니다.

Features

Output Current up to 1 A

Low Dropout Voltage ( 700mV at 1A Output Current )

Three Terminal Adjustable or Fixed 1.5V, 1.8V, 2.5V, 2.85V, 3.0V, 3.3V, 5.0V

2.85V Device for SCSI-II Active Terminator

0.04% Line Regulaion, 0.1% Load Regulation

Very Low Quiescent Current

Internal Current andTerminal Limit

Logic-Controlled Electronics Shutdown

Surface Mount Package SOT-223 & TO-263 (D2-Pack)

100% Thermal Limit Burn-In

Applications

Active SCSI Terminators

Portable/Plan Top/Notebook Computers

High Efficiency Linear Regulators

SMPS Post Regulators

Mother B/D Clock Supplies

Disk Drives

Battery Chargers

Ordering Information

Package Type : SOT-223

Operating Temperature Range : 0℃ to +125℃

7~40V의 입력으로 깔끔하게 5V를 만들어주는 IC입니다 ^^

물론 인덕터와 대용량(?) 커패시터를 귀찮게 달아줘야해서 7805를 쓰겠다는 분이 계시겠지만!!

발열량과 효율성, 그리고 출력전류로 따져보았을때! LM2576T를 안쓰실수가 없을겁니다 ^^

데이터시트는 아래에 있습니다! 

LM2576T-5V.pdf