[I2C] The I2C-bus specification : 동작설명

4 THE I2C-BUS CONCEPT

The I2C-bus supports any IC fabrication process (NMOS,CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether it’s a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver, whereas a memory can both receive and transmit data. Inaddition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table 1). A master is the device which initiates a data transfer on the bus and generates the clock

signals to permit that transfer. At that time, any device addressed is considered a slave.

Table 1 Definition of I2C-bus terminology

TERM	DESCRIPTION
Transmitter	The device which sends data to the bus
Receiver	The device which receives data from the bus
Master	The device which initiates a transfer, generates clock signals and terminates a transfer
Slave	The device addressed by a master Multi-master
Multi-master	More than one master can attempt to control the bus at the same time without corrupting the   message
Arbitration	Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one   is allowed to do so and the winning message is not corrupted
Synchronization	Procedure to synchronize the clock signals of two or more devices

The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually micro-controllers, let’s consider the case of a data transfer between two microcontrollers connected to the I2C-bus (see Fig.2).

This highlights the master-slave and receiver-transmitter relationships to be found on the I2C-bus. It should be noted

that these relationships are not permanent, but only depend on the direction of data transfer at that time. The

transfer of data would proceed as follows:

1) Suppose microcontroller A wants to send information to microcontroller B:

· microcontroller A (master), addresses microcontroller B (slave)

· microcontroller A (master-transmitter), sends data to microcontroller B (slave- receiver)

· microcontroller A terminates the transfer

2) If microcontroller A wants to receive information from microcontroller B:

· microcontroller A (master) addresses microcontroller B (slave)

· microcontroller A (master- receiver) receives data frommicrocontroller B (slave- transmitter)

· microcontroller A terminates the transfer.

Even in this case, the master (microcontroller A) generates the timing and terminates the transfer.

The possibility of connecting more than one microcontroller to the I2C-bus means that more than one

master could try to initiate a data transfer at the same time. To avoid the chaos that might ensue from such an event -

an arbitration procedure has been developed. This procedure relies on the wired-AND connection of all I2C

interfaces to the I2C-bus.

If two or more masters try to put information onto the bus, the first to produce a ‘one’ when the other produces a

‘zero’ will lose the arbitration. The clock signals during arbitration are a synchronized combination of the clocks

generated by the masters using the wired-AND connection to the SCL line

Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line, or by another master when arbitration occurs.

5 GENERAL CHARACTERISTICS

Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a current-source or pull-up resistor (see Fig.3). When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the I2C-bus can be transferred at rates of up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode. The number of

interfaces connected to the bus is solely dependent on the bus capacitance limit of 400 pF. For information on High-speed mode master devices

6 BIT TRANSFER

Due to the variety of different technology devices (CMOS,NMOS, bipolar) which can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of VDD (see Section 15 for electrical specifications). One clock pulse is generated for each data bit transferred.

6.1 Data validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see Fig.4).

6.2 START and STOP conditions

Within the procedure of the I2C-bus, unique situations arise which are defined as START (S) and STOP (P) conditions (see Fig.5).

A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered to be busy after the START

condition. The bus is considered to be free again a certain time after the STOP condition. This bus free situation is

specified in Section 15. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical (see Fig. 10). For the remainder of this document, therefore, the S symbol will be used as a generic term to represent both the START and repeated START

conditions, unless Sr is particularly relevant. Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition.

-> START는 위의 파형과 같이 SCL이 High신호일대 SDA가 Falling 하는 경우로 slave에게 protocol이 시작됨을 알린다.

-> STOP는 SCL이 HIGH일때 SDA가 Rising 하는 경우로 Slave에게 protocol이 종료됨을 알린다.

즉, 둘다 SCL이 High일때 시작과 끝을 상승/하강 엣지로 Slave에게 알리는것이다. 그럼 반대로 SCL이 LOW레벨일때는 어떤동작을 할까? 아래의 내용을 보자.

7 TRANSFERRING DATA

7.1 Byte format

Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (see Fig.6). 

If a slave can’t receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then

continues when the slave is ready for another byte of data and releases clock line SCL.

In some cases, it’s permitted to use a different format from the I2C-bus format (for CBUS compatible devices for example). A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte. In this case, no acknowledge is generated. 

7.2 Acknowledge

Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse (see Fig.7). Of

course, set-up and hold times  must also be taken into account. Usually, a receiver which has been addressed is obliged to

generate an acknowledge after each byte has been received, except when the message starts with a CBUS

address. When a slave doesn’t acknowledge the slave address (for example, it’s unable to receive or transmit because it’s

performing some real-time function), the data line must be left HIGH by the slave. The master can then generate

either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.

If a slave-receiver does acknowledge the slave address but, some time later in the transfer cannot receive any

more data bytes, the master must again abort the transfer. This is indicated by the slave generating the

not-acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates a

STOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signal the end of data to the slave- transmitter by not generating

an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line

to allow the master to generate a STOP or repeated START condition.

-> DATA 는 SCL(클럭)이 LOW일때 SDA의 값이 변할수 있으며 SCL이 HIGH상태일대 SDA의 값이 유효하다. 

(SCL이 LOW일때 SDA의 신호를 변경할수있다는 뜻이다.)

(SCL이 HIGH일때 SDA신호가 일정해야지만 DATA값이 유효하는 뜻이기도 하다)

즉, START 비트가 출력되었고 다음 클럭의 HIGH신호일때 마스터가 SDA값을 읽거나 쓸수가 있다는 뜻이다.

또한 DATA bits는 ACK 신호와 R/W신호를 포함하고 있다.  

R/W신호 High 상태 = READ

R/W신호 LOW 상태 = WRITE

▶그렇다면? 어떻게 2개의 WIRE로 충돌없이 통신이 가능한것인가???

= 이는 통신시작을 알리는 START bit는 SDA,SCL 이 모두 HIGH일때만 발생하기때문에 이 조건이 만족하지 않으면 시작하지 않기 때문이다. 

▶ PULL-UP  저항은 왜 필요한것인가?

= 버스와 물려있는 다른 device간의 입출력 전압차를 상관없이 하나의 VCC레벨로 통합시켜버린다. (물론 적당히;;ㅋㅋ)

또한, 항상 SDA와 SCL이 HIGH상태로 유지하도록 만들어서 둘다 HIGH이면 버스상에 신호가 없으며 지금 IC2를 사용할수있는 의미가 된다.

▶ ACK신호는 왜 사용하는가?

= 데이터전달이 잘 되었는지를 확인하는데 그 목적이 있으며, 이는 반드시 처리해야하는 의무성을 지닌다.

다음 챕터의 데이터송수신의 과정을 읽게되면 이해하게 될것입니다.