[I2C] The I2C-bus specification : 기술설명

The I2C-bus specification

1 PREFACE (서문)

1.1 Version 1.0 - 1992

This version of the 1992 I2C-bus specification includes the following modifications:

· Programming of a slave address by software has been omitted.

  The realization of this feature is rather complicated and has not been used.

· The “low-speed mode” has been omitted. This mode is, in fact, a subset of the total I2C-bus specification and need not be specified explicitly.

· The Fast-mode is added. This allows a fourfold increase of the bit rate up to 400 kbit/s. Fast-mode devices are downwards compatible i.e. they can be used in a 0 to 100 kbit/s I2C-bus system.

· 10-bit addressing is added. This allows 1024 additional slave addresses.

· Slope control and input filtering for Fast-mode devices is specified to improve the EMC behaviour.

NOTE: Neither the 100 kbit/s I2C-bus system nor the 100 kbit/s devices have been changed.

1.2 Version 2.0 - 1998

The I2C-bus has become a de facto world standard that is now implemented in over 1000 different ICs and licensed to more than 50 companies. Many of today’s applications, however, require higher bus speeds and lower supply voltages. This updated version of the I2C-bus specification meets those requirements and includes the following modifications:

· The High-speed mode (Hs-mode) is added. This allows an increase in the bit rate up to 3.4 Mbit/s. Hs-mode devices can be mixed with Fast- and Standard-mode devices on the one I2C-bus system with bit rates from 0 to 3.4 Mbit/s.

· The low output level and hysteresis of devices with a supply voltage of 2 V and below has been adapted to meet the required noise margins and to remain compatible with higher supply voltage devices.

· The 0.6 V at 6 mA requirement for the output stages of Fast-mode devices has been omitted.

· The fixed input levels for new devices are replaced by bus voltage-related levels. 

· Application information for bi-directional level shifter is added.

1.3 Version 2.1 - 2000

Version 2.1 of the I2C-bus specification includes the following minor modifications:

· After a repeated START condition in Hs-mode, it is possible to stretch the clock signal SCLH (see Section 13.2 and Figs 22, 25 and 32). · Some timing parameters in Hs-mode have been relaxed (see Tables 6 and 7).

2 THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS

In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes:

· Some intelligent control, usually a single-chip microcontroller

· General-purpose circuits like LCD drivers, remote I/O ports, RAM, EEPROM, or data converters

· Application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, or DTMF generators for telephones with tone dialling. To exploit these similarities to the benefit of both systems designers and quipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips developed a simple bi-directional 2-wire bus for efficient inter-IC control. This bus is called the Inter IC or I2C-bus.

At present, Philips’ IC range includes more than 150 CMOS and bipolar I2C-bus compatible types for performing functions in all three of the previously mentioned categories. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus. This design concept solves the many interfacing problems encountered when designing digital control circuits. 

Here are some of the features of the I2C-bus:

· Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL)

· Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers

· It’s a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer · Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode

· On-chip filtering rejects spikes on the bus data line to preserve data integrity

· The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400 pF.

Figure 1 shows two examples of I2C-bus applications.

 2.1 Designer benefits

I2C-bus compatible ICs allow a system design to rapidly progress directly from a functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the I2C-bus without any additional external interfacing, they allow a prototype system to be modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.

Here are some of the features of I2C-bus compatible ICs which are particularly attractive to designers:

· Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block

diagram to final schematic.

· No need to design bus interfaces because the I2C-bus interface is already integrated on-chip.

· Integrated addressing and data-transfer protocol allow systems to be completely software-defined

· The same IC types can often be used in many different applications

· Design-time reduces as designers quickly become familiar with the frequently used functional blocks represented by I2C-bus compatible ICs

· ICs can be added to or removed from a system without affecting any other circuits on the bus

· Fault diagnosis and debugging are simple; malfunctions can be immediately traced

· Software development time can be reduced by assembling a library of reusable software modules.

In addition to these advantages, the CMOS ICs in the I2C-bus compatible range offer designers special features which are particularly attractive for portable equipment and battery-backed systems.

They all have:

· Extremely low current consumption

· High noise immunity

· Wide supply voltage range

· Wide operating temperature range.

2.2 Manufacturer benefits

I2C-bus compatible ICs don’t only assist designers, they also give a wide range of benefits to equipment

manufacturers because:

· The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pins and there are

not so many PCB tracks; result - smaller and less expensive PCBs

· The completely integrated I2C-bus protocol eliminates the need for address decoders and other ‘glue logic’

· The multi-master capability of the I2C-bus allows rapid testing and alignment of end-user equipment via external connections to an assembly-line

· The availability of I2C-bus compatible ICs in SO (smalloutline), VSO (very small outline) as well as DIL packages reduces space requirements even more.

These are just some of the benefits. In addition, I2C-bus compatible ICs increase system design flexibility by allowing simple construction of equipment variants and easy upgrading to keep designs up-to-date. In this way, an entire family of equipment can be developed around abasic model. Upgrades for new equipment, or enhanced-feature models (i.e. extended memory, remote control, etc.) can then be produced simply by clipping the appropriate ICs onto the bus. If a larger ROM is needed,

it’s simply a matter of selecting a micro-controller with a larger ROM from our comprehensive range. As new ICs supersede older ones, it’s easy to add new features to equipment or to increase its performance by simply unclipping the outdated IC from the bus and clipping on its successor.

3 INTRODUCTION TO THE I2C-BUS SPECIFICATION

For 8-bit oriented digital control applications, such as those requiring microcontrollers, certain design criteria can be

established:

· A complete system usually consists of at least one microcontroller and other peripheral devices such as memories and I/O expanders

· The cost of connecting the various devices within the system must be minimized 

· A system that performs a control function doesn’t require high-speed data transfer 

· Overall efficiency depends on the devices chosen and the nature of the interconnecting bus structure.

To produce a system to satisfy these criteria, a serial bus structure is needed. Although serial buses don’t have the

throughput capability of parallel buses, they do require less wiring and fewer IC connecting pins. However, a bus is not merely an interconnecting wire, it embodies all the formats and procedures for communication within the system.

Devices communicating with each other on a serial bus must have some form of protocol which avoids all possibilities of confusion, data loss and blockage of information. Fast devices must be able to communicate with slow devices. The system must not be dependent on the devices connected to it, otherwise modifications or improvements would be impossible. 

A procedure has also to be devised to decide which device will be in control of the bus and when. And, if different devices with different clock speeds are connected to the bus, the bus clock source must be defined. All these criteria are involved in

the specification of the I2C-bus.

결론적으로 2000년도에 발표된 2.1버전의 특징만 아시면 됩니다.

간단하게 요약하자면 ,

-오직 2가닥의 와이어만 필요합니다 (SDA-Serial Data Line, SCL-Serial Clock Line) 또한 인터페이스는 칩에 내장되어있기에 별다른 디자인이 필요하지 않습니다.

-SCL은 마스터에서 클럭소스를 OUT하는 선이며 SDA는 SCL의 클럭에 완벽히 동기화되어 실제 data가 송수신됩니다.

-Bus에 연결된 master와 slave는 소프트웨어적으로 adress접근이 가능하다면 완벽하게 연결되며 제어가 됩니다.

-다수의 마스터가 연결될수가 있으며 장치간 충돌이 있어도 감지가 가능합니다. 또한 2개이상의 마스터를 초기화해도 통신이 가능합니다.

-시리얼 8비트 데이터통신은 일반모드에서 100kbps의 속도를 FAST모드에서 200kbps, Highspeed모드에서 3.4Mbps의 속도를 가집니다.

-단일칩 필러터링으로 버스에서 발생할수있는 노이즈를 차단할수있습니다

-최대 연결이 가능한 버스는 커패시턴스가 400pF이 넘지않는다면 IC를 계속 연결할수있습니다. ATmega를 예로들면 최대 연결이 가능한 IC는 128개로 제한하고 있습니다. 이는 주소값이 7bit 가지므로 2^7=128 의 이론값에서 나온것입니다.

일단 이정도 하시면 사용에 문제는 없습니다.